1. Field of the Invention
The present invention relates to a digital TV or a digital image conference system, and more particularly to an apparatus for receiving motion pictures to reduce an external memory of a MPEG-2 decoding chip, which is a standard device in digital video transmission.
2. Discussion of the Related Art
Recently, digital TV broadcasting has been gaining more attention. Accordingly, efforts are being made to better compress and transmit video data to allow a clear and high definition screen on household TVs. Having a high compression rate of {fraction (1/40)}xcx9c{fraction (1/60)}, A MPEG-2 is primarily used as an algorithm to compress the video signals. The MPEG-2 algorithm has allowed and prompted further research to transmit digital data of high definition to households through general broadcasting channels. Accordingly, a digital TV receiver requires a MPEG-2 video decoder for reconstruction of the compressed data to the original video data of high definition.
FIG. 1 is a block diagram of a MPEG decoding system in the related art. Referring to FIG. 1, a transport (TP) decoder 101 selects a program signal from a plurality of programs included in one channel, and separates the selected signal packet into audio bit stream and video bit stream to output the separated video bit stream to a video decoder 102 through a data bus. The video decoder 102 eliminates overheads such as various header information and start codes, from the video stream and performs a variable length decoding (VLD). The video decoder 102 also performs an inverse quantization, an inverse discrete cosine transformation (IDCT), and motion compensation using motion vectors to restore pixel values of the original screen and to output the pixel values to a video display processor (VDP) 103. The VDP 103 either re-sorts or outputs the data of restored pixel values in accordance with the picture coding types.
The video decoder system based on MPEG-2 uses an external memory 105, which comprises a buffer and two or more frame memories for temporarily storing a bit stream. Here, a dynamic RAM (DRAM) is usually used as the frame memory. In a video decoder, the role of the external memory 105 is mainly divided into the following categories: writing and reading data for video decoding; reading data required for motion compensation; and writing and reading of decoded data to be displayed. The data are exchanged under the control of a memory control unit 104.
However, to decode a video data of MPEG-2 MP@HL, the amount of data increases by approximately six times more than that of MPEG-2 MP@ML. Thus, more than 93 Mbit of data needs to be processed per second, requiring a large memory and a high speed data transmission. Also, a bit-buffer size of about 10 Mbit with maximum bit rate of about 80 Mbit is required to support the MP@HL mode within the standard MPEG-2. Accordingly, a MPEG-2 video decoder based on the conventional 16 Mbit of DRAM requires an external memory of about 96-128 Mbit. This means an escalation in the cost of the memory.
For competitiveness of the product cost as well as for an appeal to consumers, it is critical to retain a motion picture of high definition while reducing the price of the memory. Moreover, in view of the current trend of providing diverse kinds of on-screen display (OSD) and services, additional memories would probably be required in the future. For example, recent MPEG-2 video decompression system provides diverse services by decoding and simultaneously displaying multiple types of video signals. In such case, the system should be able to decode multiple video signals using a limited memory.
In consideration of the limits and costs of a memory as well as the bandwidth of a data bus, an efficient memory reduction apparatus is required to minimize the loss of high definition video signals in a video decoding chip. As a result, several methods have been suggested for that purpose.
One memory reduction algorithm in the related art is mounted inside a video decoding chip and suggests an adaptive differential pulse coded modulation (ADPCM) having a reduction rate of 50%. Another memory reduction algorithm in the related art which is mounted inside a video decoding chip eliminates spatial redundancy using a vector quantization (VQ) having a reduction rate of 75%. Moreover, a compressing manner utilizing a filtering/down-sampling in a DCT frequency region has been suggested.
However, in the above methods, either the complicated texture is degraded in the reduction rates of 50xcx9c75% or it is difficult to provide a high definition MPEG-2 MP@HL with a high color components. In other words, a relation between the motion picture of high definition and the reduction rate is not only inverse proportion but also requires a very complicated algorithm. Accordingly, it is difficult to implement such a complicated algorithm by means of an integrated circuit(IC). Furthermore, implemented a complicated algorithm poses a problem of increasing the number of gates.
An object of the present invention is to solve at least the problems and disadvantages of the related art.
An object of the present invention is to provide an efficient apparatus for receiving and processing motion pictures with high definition.
Another object of the present invention is to efficiently reduce an external memory of a MPEG-2 video decoder.
A further object of the present invention is to provide an efficient apparatus for receiving motion pictures to compress and store video-decoded data in an external memory.
A still further object of the present invention is to provide an apparatus for receiving motion pictures to restore data which has been compressed and stored in an external memory.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
To achieve the objects and in accordance with the purposes of the invention, as embodied and broadly described herein, the apparatus for receiving motion pictures according to the present invention comprises a video decoder for performing a VLD of input video stream in macro-block units, restoring pixel values to the original screen after performing an inverse quantization, and motion compensating using motion vectors; an external memory for decoding the video signals; a compression unit for dividing a macro-block of the video-decoded pixel values into a plurality of sub-blocks, and compressing the pixel values video-decoded in sub-block units for storage in the external memory; a decompression unit for reading the pixel values compressed by and stored in the external memory; and a memory control unit for controlling compression/decompression of the data and storage of the data in the external memory.
The compression unit comprises a deviation calculation unit for calculating the standard deviation of the video-decoded data in a sub-block unit, a buffer for temporarily storing the video-decoded data in a macro-block unit; an ADPCM compression unit for outputting the first row in each sub-block into the original uncompressed pixel value, and coding the difference between a predicted pixel value and the current pixel value with respect to the remaining rows to adjust the quantization interval by applying the standard deviation; and a first-in first-out memory (FIFO) for adjusting the data rate between the video decoder and the external memory by temporarily storing an output of the ADPCM compression unit.
The adaptive quantization unit of the ADPCM compression unit is characterized by differentiating the quantization levels with respect to each luminance signal and color signal.
The deviation calculation unit of the ADPCM compression unit comprises a variance computing unit for obtaining variance in a sub-block unit after receiving a plurality of pixels in parallel within one clock; a deviation computing unit for obtaining standard deviation by taking a square root over the variance computing unit; a deviation control unit for outputting the least bit into zero if the standard deviation output from the deviation computing unit is a standard deviation of the luminance signal, and outputting the least bit if the standard deviation output from the deviation computing unit is a standard deviation of the color signals; a deviation adjustment unit for limiting the scope of standard deviation of the luminance signal and color signals output from the deviation control unit; a comparator for obtaining a maximum value of the prediction error from each difference signal of the plurality of pixels input to one clock in parallel, and comparing the obtained value with the predetermined threshold value; and an ultimate deviation output unit for outputting an ultimate deviation by adding a luminance signal offset or a color signal offset to the standard deviation of the deviation adjustment unit if the maximum value of the prediction error is determined to be greater than the predetermined threshold value by the comparator, and outputting an ultimate deviation to be the deviation of the deviation adjustment unit if the maximum value of the prediction error is determined to be less than the predetermined threshold value by the comparator.
The FIFO comprises a code FIFO for storing the code value quantized by the adaptive quantization unit; and a barrel shifter for bit-sorting the standard deviation and quantization code when writing/reading in the external memory. Also, the external memory is characterized in that the synchronous DRAM (SDRAM) is allocated to have different bank addresses in upper and lower slices thereof. Moreover, the memory control unit is characterized by generating a signal so that the data stretched over two slices are read by a memory interleaving access method when the compression unit reads data from the memory.
The present invention has a data processing structure for compressing video-decoded data in an ADPCM manner to be stored in the external memory to facilitate motion compensation in a macro-block unit and to retain motion picture of high definition. When compressing the data, each macro-block is selected after being divided into sub-blocks of 4xc3x978 size. The first row of each block is stored as the original pixel value without being compressed, and ADPCM is performed for each of the remaining rows. At this stage, compression is performed by applying the adaptive standard deviation to quantization, and the resultant value is stored.